Automated out-of-band flow control using CTS/RTS and DSR/DTR |
Compliant with PCI Express base specifications revision 1.0a |
Includes a full profile and low profile/half-height bracket |
Native single chip design |
On chip 256-byte depth FIFO in transmit/receive path of each port |
Single-Lane (x1) PCI-Express with throughput up to 2.5Gbps |
Supports data transfer rates up to 250Kbps on each port |
Supports hardware and software flow control |